United States Patent
Potter et al.
Patent Number: 4,899,342
Date of Patent: Feb. 6, 1990

METHOD AND APPARATUS FOR OPERATING MULTI-UNIT ARRAY OF MEMORIES Primary Examiner -- Michael R. Fleming
Atttorney, Agent, or Firm -- Pennie & Edmunds


INVENTORS: David Potter, Acton; Lawrence N. Provost, Arlington; John M. Baron, Grafton; David Stefanovic, Allston; Eric D. Sharakan, Brighton; David A. Sheppard, Cambridge; Marshall A. Isman, Newton, all of Mass.
Assignee: Thinking Machines Corporation, Cambridge, Mass.
Appl. No.:
Filed:
Int. Cl.(4):
U.S. Cl.:
Field of Search
150,814
Feb. 1, 1988
G06F 11/10
371/10.1; 371/40.1
371/10, 38, 10.1, 10.2, 371/10.3, 37.1, 40.1, 40.2, 40.3, 40.4; 365/200, 201; 364/200, 900


References Cited
U.S. Patent Documents
4,646,304
2/1987
Fossati
371/38
4,654,847 3/1987 Dutton 371/10
4,703,453 10/1987 Shinoda 371/10
4,710,934 12/1983 Traynor 371/38

ABSTRACT

A method and apparatus are disclosed for operating a multi-unit memory system so that one of such units may be readily placed in service. The system comprises an error correction code (ECC) generation circuit, a plurality of read/write memory units and at least one spare read/write memory unit. The ECC circuit generates an error correction code for each block of data to be stored in the system and supplies this code along with the block of data to the memory units for storage. The system further comprises means for generating from a sequence of blocks of data and associated error correction codes retreived from these memory units a sequence of bits which correct an error in the information retrieved from one memory unit and means for writing this sequence of correction bits to the spare read/write memory unit. Advantageously, the system also comprises means for rewriting the sequence of correction bits to a memory unit after a faulty memory unit has been repaired or replaced. Preferably, the sequence of correction bits is generated by the same ECC circuit which generates the error correction codes; and the sequence of correction bits is connected to the spare memory unit, a repaired unit, or a replacement unit through an array of multiplexors.

18 Claims, 2 Drawing sheets




And so on... 8 pages in all.

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